standard features ? 5.0v low-leakage cmos transistors 17v and 40v high-voltage ldmos transistors high-density, double-poly memory cell isolated nmos and ldmos transistors analog resistors dual poly capacitor mono-silicon capacitors 3 layer metal isolated and folded bond pads applications power management integrated circuits high performance mixed-si gnal with embedded memory motor/motion control automotive monitor and control circuitry description atmel?s AT35700, 0.35um, high-voltage cmos foundry technology process was developed for mixed-signal and power management applications. the technology has ldmos transistors capable of 17v and 40 v operation and has 5.0v low-leakage cmos transistors. the low-leakage cmos has been engineered to minimize sub- threshold leakage currents making this te chnology ideal for portable electronic devices. isolated nmos and ldmos transi stors are included to minimize circuit noise. a large selection of on-chip analog resistors and capacitors are included to reduce off-chip component requirements. the technology supports placement of esd and i/o transistors under the bond pads, thus minimizing the die size. included is atmel?s reliable double-poly, high-density memory cell. the cell can be used to create parallel eeprom, seri al eeprom or pseudo flash memory designs. having embedded eeprom provides large data storage capability as required in monitor and control applications and eliminates the need for additional memory chips. 0.35um, 40.0v hv cmos foundry technology AT35700 preliminary 5166a?hvcmos?5/06
2 5166a?hvcmos?5/06 AT35700 [preliminary] atmel?s AT35700 0.35um hv cmos foundry process specifications table 1. cmos specifications note: 1. see drm table 2. resistor specifications table 3. capacitor specifications cmos drawn size (um) v t (v) bvdss (v) max op (v) tox (angstrom) lv nmos 0.49 0.85 >6 6 110 lv pmos 0.49 -0.9 <-6 -6 110 hv nmos in substrate/no vt ii 1.68 0.05 >15 10 275 hv nmos in substrate/vt ii 1.33 0.6 >12 10 275 hv nmos in hv p-well/no vt ii 1.54 0.3 >14 10 275 hv pmos in hv n-well/vt ii 1.12 -0.85 <-12 -12 275 hv pmos in lv p-well 1.505 -0.85 <-16 -12 275 hv bn+ nmos in substrate/no vt ii 2.765 -0.15 >16 16 275 hv bn+ nmos in substrate/vt ii 2.66 0.55 >16 12 275 hv bn+ nmos in hv p-well/no vt ii 2.765 0.3 >16 16 275 isolated nmos (nmos in svnwell) 0.49 0.85 >6 6 110 ldnmos note 1 note 1 >40 40 275 ldpmos note 1 note 1 <-40 40 275 resistor n-well n-ldd poly 2 bn+ in poly 1 n+ in poly 2 p+ in poly 2 ( ? / ? ) 3200 1500 135 300 100 170 capacitor capacitance (ff/um 2 ) equivalent thickness (a) max op (v) poly2 to poly1 (ono) 1.55 215 16 poly2 to bn+ (sio2) 1.15 290 16 poly2 to bn+ (sio2) 2.5 130 6 poly2 to poly1 40 poly2 to lv n-well 3 110 6
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